confirmed

suggested

SpeedStep

Intel Platform IDs

The IA32_PLATFORM_ID MSR (0x17) is present on all family 6 and later intel CPUs starting with Deschutes (family 6, model 5) to provide a finer level of identification than provided by CPUID. It is only intended for use by microcode loaders to allow different updates for different platforms/packages. Intel don't seem to provide any information on how to map the ID to a platform/package, and I couldn't find much info on the web -- hence this page. By cross-referencing microcode update headers with Specification Updates and testing a selection of CPUs it should be possible to determine the mapping.

The actual platform ID is only bits 50-52 of MSR 0x17, which are interpreted as a 3-bit number. For microcode updates the number indicates a bit position in a byte of the header. When used in conjunction with the level 2 (and in a few cases also level 3) cache size, the platform ID forms a more precise identification method than the CPUID brand ID (the brand ID may still be needed to determine Xeon DP vs. MP).

Family 6 mobile platforms seem to have odd IDs (bit 50 == 1), wheras desktop platforms are even (bit 50 == 0). For Coppermines (and others?) MSR 0x17 also encodes the current multiplier and can be used to determine if SpeedStep is present, see below for more information.

According to intel (here) bit 28 being set on Conroe and later family 6 chips denotes a mobile platform. Bit 21 in MSR 0x2C apparently serves the same function on Northwood and later family F chips, although they state that there are exceptions (family F model 4 with CPUID.1.EBX[23:16] > 2 is given as an example).

If you can add to or correct any of this information then please email x86test@vortex.prodigynet.co.uk.

Confirmed Values

The following were provided by email or infered from reports on the web:

Suggested Values

The values below are incomplete and many may be incorrect. They were determined by comparing microcode update headers with the available packages for each stepping in Specification Updates. Confirmed values are in bold.

• P6 [family 6, model 1]
  • all socket 8, platform ID not supported.
• P6T (Deschutes core) [family 6, model 3, step 2, type 1]
  • 0: socket 8
• Klamath [family 6, model 3, step ≠ 2, type 0]
  • all slot 1, platform ID not supported.
• Deschutes / Tonga / Covington / Drake [family 6, model 5]
  • 0: slot 1
  • 1: ???
  • 2: slot 2
  • 3: ???
  • 5: ???
  • 7: ???
• Mendocino [family 6, model 6, step < 8]
  • 0: slot 1 (SEPP, 540-ball PBGA chip)
  • 4: socket 370 (PPGA)
• Dixon [family 6, model 6, step ≥ 8]
  • 1: mini-cartridge (615-ball FC-BGA chip)?
  • 3: MMC1/2 (615-ball FC-BGA chip with 82433DX (MMC1) or 82443BX (MMC2) northbridge)
  • 5: 615 contact FC-BGA (BGA) with optional μPGA interposer (Micro-PGA)
• Katmai / Tanner [family 6, model 7]
  • 0: slot 1
  • 2: slot 2
• Coppermine [family 6, model 8]
  • 0: slot 1 (495-ball FC-BGA chip)
  • 2: slot 2 (495-ball FC-BGA chip)
  • 3: MMC1/2
  • 4: socket 370 (FC-PGA / FC-PGA2)
  • 5: 495 contact FC-BGA (BGA2) with optional μPGA interposer (μPGA2)
  • 7: 479 contact FC-μPGA / FC-BGA
• Banias [family 6, model 9]
  • 4: socket 370 (FC-PGA2) ???
  • 5: 479 contact FC-μPGA / FC-BGA
  • 7: ???
• Cascades (Coppermine Xeon with 1/2MB L2) [family 6, model A]
  • 2: slot 2 (495-ball FC-BGA chip)
• Tualatin [family 6, model B]
  • 4: socket 370 (FC-PGA2)
  • 5: 479 contact FC-μPGA / FC-BGA
• Dothan [family 6, model D]
  • 5: 479 contact FC-μPGA / FC-BGA
• Yonah / Sossaman [family 6, model E]
  • 5: socket M / 479 (FC-μPGA) (new pinout)
• Conroe / Allendale / Woodcrest / Merom / Kentsfield / Clovertown [family 6, model F]

  platform IDs provided by Ray Hinchliffe, author of SIV.

  • 0: socket 775 (FC-LGA6) Conroe/Allendale
  • 2: socket J / 771 (FC-LGA6)
  • 4: socket 775 (FC-LGA6) Kentsfield
  • 5: 479 contact FC-μPGA ?
  • 6: socket J / 771 (FC-LGA6) (Clovertown)
  • 7: 479 contact FC-μPGA
• Conroe-L / Merom-L [family 6, model 0x16 (22 decimal)]
  • ?: socket 775 (FC-LGA6)
  • 2: 479 contact FC-μBGA (celeron 220)
  • 7: 479 contact FC-μPGA
• Yorkfield / Penryn [family 6, model 0x17 (23 decimal)]
  • ?: socket J / 771 (FC-LGA6)
  • ?: socket 775 (FC-LGA6)
  • ?: socket P / 479 (FC-μPGA)
• Willamette / Foster [family F, model 0/1]
  • 0: socket 423 (OLGA on PGA interposer)
  • 1: socket 603 (OLGA on μPGA interposer)
  • 2: socket 478 (FC-PGA2)
• Northwood / Prestonia / Gallatin [family F, model 2]
  • 0: socket 775 FC-LGA4?
  • 1: socket 603 (OLGA on μPGA interposer) / socket 604 (FC-PGA2)
  • 2: socket 478 (FC-PGA2)
  • 3: socket 478 (FC-PGA) mobile
  • 4: socket 775 (FC-LGA4)?
• Prescott / Nocona / Irwindale / Cranford / Potomac / Smithfield / Paxville [family F, model 3/4]
  • 0: socket 604 (FC-PGA4) (Nocona at least)
  • 1: socket 604 (FC-PGA4) (Potomac 667MHz FSB only?)?
  • 2: socket 478 FC-PGA2
  • 3: ???
  • 4: socket 775 (FC-LGA4)
  • 5: socket 604 (FC-PGA4) (Cranford 667MHz FSB only?)?
  • 7: ???
• Cedar Mill / Presler / Dempsey / Tulsa [family F, model 6]

  platform IDs 0,2 provided by Ray Hinchliffe, author of SIV.

  platform IDs 1,5 from Xeon 71xx Specification Update (314554-001).

  • 0: socket J / 771 (FC-LGA6)
  • 1: socket 604 (FC-PGA6) Xeon MP 7130/7140 (8/16MB L3)
  • 2: socket 775 (FC-LGA6)
  • 4: ???
  • 5: socket 604 (FC-PGA6) Xeon MP 7110/7120 (4MB L3)

Packaging Terminology

Interface types:

• PGA: Pin Grid Array (nominal 0.1in/2.54mm spacing)
• micro-PGA/mPGA/μPGA: PGA with small grid spacing (nominal 0.05in, 1.27mm)
• LGA: Land Grid Array, package has flat lands instead of pins (nominal 0.05in/1.27mm spacing).
• BGA: Ball Grid Array, LGA package with solder balls pre-applied to lands for easy surface-mount assembly.

Note that a surface-mounted LGA package is the same as a surface-mounted BGA package so the names can be used interchangably when refering to an assembled module.

Substrate abbreviations:

• C: Ceramic e.g. CPGA for 386,486,P54,P55
• P: Plastic e.g. PPGA for P54,P55,S370 mendocino, PLGA/PBGA for slot-1 klamath/deschutes/mendocino
• O: Organic e.g. OPGA for coppermine etc., OLGA for willamette etc.

Package styles:

• FC: Flip-Chip, die mounted upside-down with underside of die exposed
• FC-2: FC with Integral Heat Spreader (IHS) covering die
• FC-4: similar to FC-2, used on prescott based P4/PD/Xeon chips
• FC-6: similar to FC-2, used on cedar-mill based P4/PD/Xeon and conroe based C2D/Xeon chips

Usually either a substrate abbreviation or package style is used in a name, but not both – the other is assumed e.g. FC-PGA usually implies an organic substrate. The micro/m/μ prefix on the interface type is often dropped when it is obvious e.g. when the socket type is specified.

Coppermine SpeedStep detection

SpeedStep was introduced for the Mobile Pentium III to allow the processor to be switched between two multiplier/voltage states. However, SpeedStep was not used on all mobile P3s, and was not used at all on celerons. Detecting the presence of SpeedStep on a coppermine (family=6, model=8) without actually attempting a speed transition requires:

• check it's a P3: L2 cache = 256KB.
• check it's a mobile: platform ID is odd [3 = MMC, 5 = μPGA2, 7 = FC-μPGA/FC-μBGA].
• SpeedStep present if either of bits 56,57 of platform ID MSR (0x17) are set.

This last point is taken from the linux cpufreq SpeedStep driver (linux/arch/i386/kernel/cpu/cpufreq/speedstep-lib.c). I recently got a load of mobile coppermine chips, so I thought I'd have a look at the platform ID MSR values to check that this test makes sense.

¹ Chips with SpeedStep have two possible multipliers, those without only have a single multiplier.

² In all cases bits [1:47], 55 and 63 of MSR 0x17 were all zero.

³ Bits [62:59] appear to represent the current multiplier in the same way as bits [25:22] of the Power-on Configuration MSR (0x2a).

⁴ Bit 57 is 1 on chips with SpeedStep. It appears to be 0 on all other chips except desktop celerons.

⁵ Bit 58 appears to be 1 on all celerons and 0 on all P3s.

⁶ Platform ID

⁷ Bits [48:47] appear to be quite random, they even differ for chips with the same sSpec!

top

confirmed

suggested

SpeedStep